1. Field of the Invention
The present invention relates to a data driven type information processing apparatus and, more specifically, to a data driven type information processing apparatus including at least one data driven type processor, a plurality of memories and a router for connecting these.
2. Description of the Related Art
Recently, higher speed of operation of processors has been in strong demand in the field of image processing. Parallel processing is considered one promising means to meet such a demand of higher speed of operation of the processors. Among architectures suitable for parallel processing, an architecture called data driven type architecture is especially attracting attention.
In a data driven type processor, process proceeds in accordance with a simple rule, that is, "process is carried out as soon as all input data necessary for the process are collected and resources such as an arithmetic unit necessary for that process are allocated." A mechanism for detecting the collection of the input data (firing) is one of the necessary technique for implementing the architecture. A system which allows only one set of input data for a certain process at the time of detecting firing is referred to as a static data driven type system, while a system which allows two or more sets of input data is referred to as a dynamic data driven type system.
The static data driven type system cannot sufficiently cope with processing of time sequential data such as video signal processing, and it may be necessary to employ dynamic architecture system. At this time, since there are plural sets of input data for a certain process, it is necessary to introduce a concept of generation identifier or the like for identifying the plural sets of input data. In this specification, the generation identifier will be referred to as a generation number.
One example of the data driven type image processing apparatus suitable for video processing is disclosed in "An Evaluation of Parallel-Processing in the Dynamic Data-Driven Processor", (Information Processing Society of Japan, Microcomputer Architecture Symposium, Nov. 12, 1991).
FIG. 1 is a block diagram showing a structure of a conventional data driven type information processing apparatus suitable for video processing. The data driven type information processing apparatus of FIG. 1 includes a data driven type processor 51 suitable for video processing and a video memory 52.
Data packets having generation numbers allotted corresponding to the time-wise order of input are time sequentially input to data driven type processor 51 through a data transmission path 53. Data driven type processor 51 stores content of processing set in advance. Data driven type processor 51 processes the input data packets based on the preset content of processing.
When data driven type processor 51 accesses video memory 52 based on the preset content of processing (for example, when it refers to or updates the content of video memory 52), a data packet is provided to video memory 52 through data transmission path 54. A data packet output from video memory 52 as a result of that access is transmitted to data driven type processor 51 through a data transmission path 55. After the processing of the input data packet, data driven type processor 51 externally outputs the processed data packet through a transmission path 56.
FIG. 2 shows an example of a field configuration of a data packet input through data transmission path 54 to video memory 52. The data packet includes an instruction code (a), a generation number (b), data 1 (c), data 2 (d) and a processor number (e).
The instruction code (a) indicates the content of processing with respect to video memory 52. The content of processing includes, for example, reference to or updating of the contents in video memory 52. The generation number (b) is an identifier allotted, at the time of input, to the data packet input to data driven type processor 51 through data transmission path 53 in accordance with the order of input time sequence. Data driven type processor 51 utilizes the generation number (b) for matching of data. In video memory 52, an address to be accessed is determined in accordance with the generation number (b).
Data 1 (c) and data 2 (d) are operand data interpreted in accordance with the content of instruction code (a). When the instruction code (a) indicates update of video memory 52, for example, data 1 (c) is the data to be written to video memory 52, and data 2 (d) does not have any meaning. If the instruction code (a) indicates reference to video memory 52, data 1 (c) and data 2 (d) are meaningless.
The processor number (e) is an identifier indicating, when the data driven type information processing apparatus includes a plurality of data driven type processors, the data driven type processor of which processor number is to be used for processing the data packet.
Here, data driven type processor 51 of FIG. 1 has a processor number PE#0 allotted thereto, and video memory 52 has a memory number VM#0.
In the data packet shown in FIG. 2, the instruction code (a) includes 8 bits, the generation number (b) includes 24 bits, data 1 (c) includes 12 bits, data 2 (d) includes 12 bits, and the processor number (e) includes 10 bits.
FIG. 3 shows an example of a field configuration of a data packet output from video memory 52 to data transmission path 55. The data packet includes an instruction code (f), a generation number (g), data i (h) and a processor number (i).
In the data packet, the instruction code (a), the generation number (b) and the processor number (e) of the data packet shown in FIG. 2 are stored as they are, as the instruction code (f), the generation number (g) and the processor number (i). The result of access to the video memory 52 is stored as data 1 (h).
FIG. 4 shows an example of detailed configuration of the generation number (b). As shown in FIG. 4, the generation number (b) includes a field address FD#, a line address LN# and a pixel address PX#.
In the example of FIG. 4, 3 bits are allotted for specifying the number of plane or field of video memory 52, 11 bits are allotted for specifying resolution in the vertical direction or lines of one plane, and 10 bits are allotted for specifying resolution in the horizontal direction or pixels of one plane. As for the allotment of bits, any number of bits may be set provided that the number of bits do not exceed the number of bits allotted for the generation number (b), that is, 24 bits in this example.
FIG. 5 shows logical structure of video memory 52 based on the grouping example of the generation number (b) shown in FIG. 4.
The logical structure of video memory 52 shown in FIG. 5 includes 8 video memories specified by a field address FD# of 3 bits. Each video memory includes 2.sup.11 =2048 lines in the vertical direction corresponding to the line address LN# of 11 bits shown in FIG. 4. Each line includes 2.sup.10 =1024 pixels corresponding to the pixel address PX# of 10 bits shown in FIG. 4.
A generation number has already been allotted, at the time of input, to the data packet input to data driven type processor 51 in accordance with the order of the input time sequence. If an address to be accessed of video memory 52 is determined based on the generation number, the access point starts from the upper left point of the first one of the video memories and moves to scan in the horizontal direction. When scanning of one line is completed, the access point moves to the left end of the immediately succeeding line. When scanning to the lower right point of the first one of the video memories is completed, the access point moves to the upper left point of the second one of the video memories. In the similar manner, the access point of the video memory moves to scan successively. When scanning to the lower right point of the last video memory, in this example the eighth video memory is completed, the access point returns to the upper left point of the first one of the video memories, and the same operation is repeated.
Now, in the conventional system shown in FIG. 1, only one data driven type processor 51 can be used. If the amount of required arithmetic operation is too large, the processing capability of only one data driven processor 51 may not be sufficient. Conversely, even if the data driven type processor has high operating capability, the capacity of processing of the system as a whole is defined or limited by the capacity of processing of the video memory 52. More specifically, the capacity of processing is limited in the conventional data driven type information processing apparatus shown in FIG. 1 since it includes only one data driven type processor 51 and only one video memory 52. Therefore, it may be preferable to provide a system including a plurality of data driven type processors or a plurality of video memories, or both.
However, in that case, if data packet output from the data driven type processors are branched to a plurality of video memories based on the generation numbers in the data packets, the destination of the data packet is determined by the order of input, and therefore the data packets cannot be transmitted to a desired video memory. Accordingly, in such a data driven type image processing apparatus in which access is dependent on the generation number of the data packet, it has been difficult to distribute processes by using a plurality of video memories.
In addition, it is also difficult to provide data packets output from the video memories to the target data driven type processors.
In such a multiprocessor system or in a system including a plurality of memories, if access not only to the address designated by the generation number but also to the neighborhood thereof and a desired address having a prescribed relation with the designated address in each video memory is enabled, it would be very convenient for an image processing system in which such a manner of accessing is used frequently. Since the target address is designated by the generation number as described above in the conventional system, such accessing has been impossible, and therefore a system allowing such processing with higher efficiency has been desired.